The semiconductor Field Effect Transistor (FET), fabricated typically as a metal oxide semiconductor (MOSFET) structure on a silicon substrate or as a Gallium Arsenide (GaAsFET) device on a Gallium Arsenide substrate, is the building block of modern digital electronics. For example, memory cells for the storage of binary information and logic gates for the processing of digital data streams both use FETs as the primary components.
A review of the cell structures of various prior art memory devices follows. Some of these, such as leading volatile memory technology (i.e. memory which is lost when power is not applied, such as in a dynamic random access memory (DRAM)) use conventional semiconductor FET structures and capacitors in their cell designs. A number of alternative memory technologies that are nonvolatile (i. e. memory is retained when power is not applied) use magnetostatic coupling and magnetoresistors comprised of ferromagnetic elements to effectuate a data storage function. In addition, a recent non-volatile device proposed by the present applicant (see U.S. Pat. No. 5,432,373) using a magnetic spin transistor with one or more passive elements is also reviewed.
Finally, a brief review of the operation of typical logic gates based on conventional FET technology is also provided.
Cell Structures Used In Conventional Volatile Memory Devices
In the case of memory cells used in DRAMs, the most common commercial cell consists of only two elements, a capacitor for data storage and a field effect transistor (FET) for isolation from the array. This cell is popular because the cell size can be made small, resulting in a high packing density and a relatively low production cost. The storage element is a capacitor, and the two stable states representing the binary data “1” or “0” can be, for example, the states with stored charge Q or with stored charge 0. Every cell is connected to an array of write and read wires, also called “bit” and “word” lines. Since one capacitor linked together with other capacitors in an array will lose its charge to its neighbor, the capacitor of each cell is connected to a transistor within that cell so as to be isolated from the array. When the transistor is “on” there is a low resistance to a write or read wire so that an applied voltage can charge the capacitor during a write process or a sense circuit can determine the stored charge during a read process. When the transistor is “off,” a high impedance to the write or read wire isolates the capacitor electrically from any other element in the array.
Typically, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) for use in a DRAM is fabricated by standard lithographic processing techniques on a silicon substrate. The oxide that isolates the gate from the channel is highly insulating, so that the metallized gate has a capacitance to the rest of the device. In some designs the gate capacitance is used as the storage capacitance. Reading is performed with a sense circuit that compares the charge (or voltage) of C with the charge (or voltage) of a standard capacitor C′ in a dummy cell. Readout voltages are the order of 10 to 100 mV and the stored charge Q is the order of a million electrons.
The conventional DRAM memory device, however, suffers from a number of operational and physical drawbacks. For one, the memory is volatile. Unavoidable leakage currents discharge the capacitor so that each cell must be refreshed constantly, i.e. read and rewritten, approximately every few milliseconds. Furthermore, background alpha-particle radiation can induce sufficient conductance in the MOSFET to drain the capacitor spuriously, erasing the memory of that cell.
Finally, cell dimensions are not shrinking to the limit permitted by lithography because of restrictions on the capacitor and FET size. Consequently, there are limits on how dense these devices can be made using conventional techniques.
Cell Structures Used in Alternative Non-Volatile Memory Devices
Several alternative technologies can be used to make nonvolatile memory cells. Capacitive memory elements utilizing ferroelectric material as a dielectric have undergone decades of development work, but still suffer from fatigue: they cannot provide an infinite number of read/write cycles.
Several competing approaches use ferromagnetic materials. Three such technologies are reviewed below.
Magnetoresistive Random Access Memory (MRAM)
Magnetoresistive Random Access Memory was proposed a decade ago [J. M. Daughton, “Magnetoresistive Memory Technology,” Thin Solid Films 216, 162 (1992)] This device employs an array of bit and word lines. Each bit line is divided into n storage cells. Each cell is a trilayer composed of a ferromagnetic metal base layer, a nonmagnetic metal middle layer, and a ferromagnetic metal top layer. Note that the F-N-F geometry is not the same as giant magnetoresistance (GMR) structures; the layers are so thick that interfacial spin scattering at the F-N interfaces is a negligible fraction of all scattering events, and there is no exchange coupling across the N layer. The cell has length l, width w and thickness d. Looking at a cell in cross section across the width, there are two stable magnetization states determined by magnetostatic coupling, each with the magnetization of the two ferromagnetic films oriented in opposing directions: clockwise and counterclockwise.
The resistance of each cell, measured with a sense current applied along the length of the cell, is a function of the anisotropic magnetoresistance (AMR) of the F layers. It has value R1 when the magnetizations are perpendicular to the sense current (as is the case for either stable magnetization state) and R1′ if the magnetizations of the ferromagnetic layers are forced to lie parallel to the sense current. Each cell in the bit line is connected to the next cell with a conducting strip which has resistance Rc.
Columns of n word lines cross the m rows of bit lines. Each nonmagnetic word line crosses the top of a cell in each bit line. The state of cell (i,j) is written by sending current pulses of appropriate amplitude through bit line i and word line j, using the magnetic fields from the currents to cause the magnetization of the cell to orient either clockwise or counterclockwise. The contents of the cell are read by first biasing word line j with a large enough current so that fields from the current cause the magnetizations of both ferromagnetic layers to be canted to an orientation that is approximately 45 degrees away from the axis of the bit line.
In this orientation the resistance of the cell (for a sense current applied along the bit line) has a value R2 that is between R1 and R1′. Next, a sense current is applied along the bit line, and a voltage is measured across the bit line, having a value proportional to (n−1)R1+R2+nRc. Finally, a read current pulse is applied to the word line, in addition to the original bias current. The field from this current pulse changes the magnetization orientation in a direction more nearly parallel to the sense current if the initial orientation was clockwise, or in a direction more nearly perpendicular to the sense current if the initial orientation was counterclockwise. Thus, the voltage across the bit line either increases or decreases when the read pulse is applied. A sense circuit that measures changes of voltage records the positive or negative change as a “1” or a “0.”
By using a derivative sense technique, MRAM avoids the necessity of electrically isolating each cell. However, this approach for a non-volatile memory element also suffers from a number of drawbacks.
To begin with, the readout voltage is quite small and the signal to noise ratio is poor. The change in resistance that must be sensed during the read process is a small fraction of R1, and this small change must be distinguished from a background of approximately nR1+Rc. In practice, two elements are fabricated for each cell, thus doubling the signal, and the read process is repeated several times so that the final readout is taken as an average of repeated samplings, thus lowering the noise. This increases the time for a read cycle. Power dissipation is relatively large during readout because relatively large currents must be applied to long, resistive lines. Finally, errors can be introduced during readout if the bias current tips the magnetization into an unstable state.
MRAM with GMR Elements
Another conventional approach uses a magnetoresistor R as the storage element, and the cell is comprised of R, a reference resistor R′, and two or three FETs to isolate the cell from the rest of the array. The magnetoresistor R is typically a thin film ferromagnetic metal (or ferromagnetic/nonmagnetic metal multilayer) resistor with length l, width w and thickness d, and has two values, R′ and R′+δR, corresponding to two stable magnetization states.
For example, in one state the magnetization of a permalloy film might be parallel to the direction of flow of the sense current, Isense, and in the other state the magnetization might be perpendicular to Isense. For GMR elements, one state corresponds to the magnetizations ^M1 and ^M2 of F1 and F2 aligned parallel (or the magnetizations Mi of all ferromagnetic layers in a multilayer stack aligned parallel), and in the other state ^M1 and ^M2 are antiparallel (or the alternate ferromagnetic layers of the multilayer stack are antiparallel). The magnetization state is written by using the magnetic field generated by current pulses applied to an array of write lines.
The read process begins by selecting a cell. When a cell is addressed the isolating FETs are set to the “on” state by driving the appropriate word line to a high voltage. In this state the FETs conduct current with some low resistance, the order of 1000 Ω or less. A bias current Isense is then applied to both the magnetoresistor R and the reference resistor R′. A sense circuit at the end of a line of cells compares the two voltages and interprets a “1” or “0” when, for example, Isense*(R−R′)>0 or Isense*(R−R′)=0 respectively. The voltage levels corresponding to “1” (or “0”) are then amplified to TTL or CMOS levels.
The voltage Isense*δR that distinguishes a “1” from a “0” must be large enough for reliable discrimination. Since the magnetoresistive ratio δR/R′ of ferromagnetic films (or GMR multilayers) is small, 10 percent or less, the magnetoresistor must be made quite large. For example, with R=100 Ω and δR/R′=0.06, a reasonable bias current of 1 mA would produce a readout voltage difference of only 6 mV, and a poor signal to noise ratio is a characteristic of GMR cells.
This approach has several other drawbacks. A resistor occupies substantial area in a cell. Continuing the above example, the 100 Ω magnetoresistor could be fabricated using ferromagnetic materials with resistivities of about 20 μΩ-cm, with a length l=5 μm, width w=1 μm, and thickness d=0.01 μm. In addition, this cell requires the fabrication of two resistors, R and R′, thus requiring additional isolation FETs and, all together, taking up considerable space. The reference resistor cannot be placed outside the cell because the resistive difference, δR, is so small that the resistance of each memory resistor must be matched to a particular reference. Since resistance is a function of temperature, R=R(T), the reference resistor must be fabricated very near the magnetoresistor so that both resistors will always be at the same temperature, and the material for the reference resistor must be carefully chosen so that the temperature dependence of its resistivity is similar to that of the magnetoresistor. Finally, the resistance of each cell is quite large. When numerous cells are placed on a single read line, as in an array, the resistance of the read line is substantial. Since the read process uses current bias, the power dissipated in each read cycle is relatively large.
Spin Transistor Nonvolatile RAM (NRAM)
Active devices using magnetic spin transport are well known in the art. The history of spin transport begins with an experiment by Meservey [R. Meservey, P. M. Tedrow and P. Fulde, Phys. Rev. Lett. 25, 1270 (1970); P. M. Tedrow and R. Meservey, Phys. Rev. Lett. 26, 192 (1971); Phys. Rev. B 7, 318 (1973)] where it was shown that the electric current tunneling from a ferromagnetic electrode across a low transmission barrier into a superconducting detector carried a net spin polarization. A later spin injection experiment [described in several journals, including Mark Johnson and R. H. Silsbee, Phys. Rev. Lett. 55, 1790 (1985); Phys. Rev. B 35, 4959 (1987); Phys. Rev. B 37, 5312 (1988); Phys. Rev. B 35, 5326 (1988)] then demonstrated that (i) current driven across any ferromagnet-nonferromagnet (F1-N) interface carried a net spin polarization, (ii) that a nonequilibrium population of spin polarized electrons, equivalently a nonequilibrium magnetization ˜M, diffused away from the F1-N interface into N with a characteristic length equal to the classic spin diffusion length δs, and (iii) that the nonequilibrium magnetization in N affected the current flow (or the voltage developed) at the N-F2 interface of a second ferromagnetic film.
The idea of incorporating the spin injection effects to semiconductors was mentioned in the art even before the spin injection experiment by the present applicant proved the validity of the phenomenon. Indeed, Aronov [A. G. Aronov, Sov. Phys. JETP 24, L32 (1976)] proposed that a current driven from a ferromagnet into a semiconductor would be spin polarized, and that the spin polarization of the current in the semiconductor (N) would be maintained over a length scale of a diffusion length. However, to date applicant is unaware of any known successful implementations of these proposals.
Datta and Das, citing the spin injection experiment performed by the applicant, and noting the long spin diffusion lengths measured in aluminum (δs approximately 0.5 mm at low temperature), proposed [S. Datta and B. Das, Appl. Phys. Lett. 56, 665 (1990)] a device illustrated in FIG. 2 wherein spin injection is extended to a FET-like structure: iron contacts are employed as the source and drain and the gate voltage was to be used to modulate the source-drain current allowing the device to perform as a current modulator. According to their proposed device a nonmagnetic metal gate 174 is fabricated on a Schottky (or an insulating) barrier 176 on top of a layer of InAlAs 178 that is grown on an InGaAs substrate 180. The InAlAs—InGaAs interface forms a high conductance Two Dimensional Electron Gas (2DEG) 182 region that acts as the conducting channel between source and drain, which are thin iron films 170 fabricated on either side of the gate 174 and in contact with the 2DEG 182. The magnetizations, ^Ms 184 and ^Md 186, of the source and drain ferromagnetic films are always aligned in parallel and along the ^x direction. The source provides spin polarized electrons to the channel with the spin axes of the electrons oriented parallel to the magnetization of the source and drain, along ^x. Because of the spin injection effect the source—drain conductance is proportional to the projection of the spin orientation of the polarized electrons reaching the drain on the orientation of the drain magnetization. A voltage Vg 172 applied to the gate 174 generates an electric field along ^z along with an associated effective magnetic field along ^y, and causes the spin axis of each electron to precess [refer to a description of the Rashba effect in the above article by Datta and Das]. Thus, the orientation of the spin axes of the current carrying electrons relative to the magnetization 186 of the drain is a function of gate voltage 172: the source-drain conductance (and current) is modulated periodically as the gate voltage is monotonically increased, and the device proposed by Datta and Das functions as a current modulator.
The Datta and Das device, however, has not yet been sucessessfully fabricated and demonstrated, and the concept has never been adapted to be used as a conventional FET because a Schottky barrier at the semiconductor-iron interface damages device performance by introducing large resistances at the source and drain. It is also likely (though unproven) that the Schottky barrier acts to impede the flow of spin polarized electrons by randomizing the spin orientation of each electron. Neither has the Datta and Das device concept been adapted to be used as a memory element because the magnetizations ^Ms and ^Md were locked in a parallel configuration. Furthermore, the polarized spins were injected with orientation along ^x so that they would precess under the influence of the effective magnetic field (associated with the gate voltage) along ^y, and the length of the 2DEG conducting channel was designed to be sufficiently long that the spin polarized electrons could accumulate large phase angles as a result of their precession. In practice, precession under the influence of a field along ^y leads to randomization of spin orientation and acts to destroy the knowledge of the initial state of the spin polarized electron; therefore the information of the memory state (of the source or drain) is lost.
A replacement for conventional semiconductor devices was proposed by the present applicant in connection with a device known as the bipolar spin transistor. This device and related modifications is described in Mark Johnson, “The All Metal Spin Transistor,” I.E.E.E. Spectrum Magazine, Vol. 31 No. 5 p. 47 (1994); and Mark Johnson, “The Bipolar Spin Transistor,” Science 260, 320 (1993). This device is depicted in FIG. 1, with F1 150 and F2 152 arranged on one side of a bulk sample of aluminum 154. F1 150 injects a source of diffusing spin polarized electrons 156 and F2 152 detects their presence. This device is a novel F-N-F structure that can be used as a circuit element in a nonvolatile memory cell and has several advantages. Since the readout voltage is bipolar, positive for ^M1 and ^M2 parallel and negative for ^M1 and ^M2 antiparallel, the discrimination between a logical “1” and “0” is relatively easy; each cell needs only a single storage element whose readout is compared with ground. Furthermore, the transimpedance of the spin transistor scales inversely with size, so the readout voltage is larger (for constant current) for smaller devices, thus promoting the shrinking of cell size.
Two characteristics of the device must be taken into consideration when using the device in NRAM. First, the device can be fabricated entirely from metals, and is therefore characterized by a low electrical impedance. Thus, to fabricate an array of such elements it is necessary to electrically isolate each element from others in the array, so that the output of any element will not be shorted to ground through a neighboring element. Second, the output voltages available from the device are less than TTL or CMOS levels, and the output must therefore be amplified before it is incorporated in TTL or CMOS circuits.
Another spin transistor NRAM cell design [Mark Johnson, “Magnetic Spin Transistor,” U.S. Pat. No. 5,432,373, issued Jul. 11, 1995] is composed of a spin transistor and one or more capacitors and resistors. The passive elements provide isolation for the spin transistor of each cell, and the readout voltage was transmitted to the end of a line of elements for amplification. A drawback of this design is that resistors and capacitors take up substantial space on a chip. Thus, a substantial portion (even a majority) of cell area is occupied by passive elements, packing densities are limited, and the unique scaling feature of the spin transistor is wasted.
Furthermore, cell isolation is not very efficient and the readout voltage can be degraded during transmission to the sense circuit, resulting in higher noise and lower readout sensitivity. More recent proposals for spin transistor memory cell designs [see applications referenced above] incorporate a spin transistor with one (or more) isolating FETs. This is a practical approach, and can achieve packing densities comparable with, or higher than, DRAM.
However, until the present invention it has been impossible to integrate the functions of nonvolatile storage and cell isolation in a single element.
FET Logic Gates
Logic operations in computing devices are typically performed with digital voltage pulses and FET gates that are linked together in an appropriate way. To provide an example that permits a brief critical discussion, a standard arrangement [Paul Horowitz and Winfield Hill, “The Art of Electronics,” Cambridge Univ. Press, Cambridge U.K. (1980); see p. 328] for an AND gate operation is depicted in FIG. 3 where each element Qi is an enhancement mode FET. Q1 10, Q2 12 and Q5 18 are p-channel FETs. A p-channel FET has a high impedance, and is therefore in the “off” state, when the gate voltage is zero or positive. It has a low impedance, and is therefore in the “on” state, when the gate voltage is lower than a threshold value below zero (where the threshold value is typically 0.5 Volt or less). Q3 14, Q4 16 and Q6 20 are n-channel FETs. An n-channel FET is “off” when the gate voltage is below ground and “on” when the gate voltage is larger than a threshold value above ground. Voltage pulses of positive or zero amplitude (HIGH or “1”; or LOW or “0”) are applied simultaneously to the inputs A 22 and B 24, and the cell operates as an AND gate in the following way.
When inputs A 22 and B 24 are HIGH (“1”+“1”), Q3 14 and Q4 16 are “on”, Q1 10 and Q2 12 are “off”, and consequently the voltage at node 26 is at LOW, i.e. at ground. Since Q6 20 is “off” and Q5 18 is “on” the voltage output (OUT) 28 is HIGH (“1”). When A 22 and B 24 are LOW (“0”+“0”), Q3 14 and Q4 16 are “off”, Q1 10 and Q2 12 are “on”, and consequently the voltage at node 26 is HIGH. Since Q5 18 is “off” and Q6 20 is “on” the voltage output (OUT) 28 is LOW, at ground (“0”). When A 22 (or B 24) is HIGH and B 24 (or A 22) is LOW (“1”+“0”), Q3 14 and Q2 12 are “on”, Q1 10 and Q4 16 are “off”, and consequently the voltage at node 26 is HIGH and the voltage output (OUT) 28 is LOW, at ground (“0”). The truth table 30 for the above operations is seen to be the same as that of an AND gate.
Although logic gates of this design are the backbone of digital electronic processing, they suffer from several disadvantages. It requires numerous FETs (six in the example of FIG. 1) to comprise the logic gate cell, and therefore the cell occupies a large area of the chip. Furthermore, the result of the Boolean process is not stored and must be synchronized with a clock cycle to be used in the next operating step, or must be sent to a separate storage cell for later recall. The above discussion was presented for complimentary metal oxide silicon (CMOS) logic devices. The transistor-transistor logic (TTL) family is based on bipolar transistors, but similar conclusions apply. In other words, the cell of a single TTL logic gate is comprised of several transistors and several resistors, and uses considerable space on a chip. It is apparent that it would be desirable to integrate the functions of logic operation and storage in a single element.